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| MK1725 Quad Output Spread Spectrum Clock Generator Description The MK1725 generates 4 high-quality, high-frequency spread spectrum clock outputs. It is designed to replace spread spectrum clock generators and a buffer in many digital consumer applications. Using ICS' patented Phase Locked Loop (PLL) techniques, the device runs from a lower frequency clock or crystal input. The MK1725 has a 16 location ROM table which provides maximum flexibility for system designers. The chip also has a power down pin which can be used to reduce power. Features * Packaged in 16-pin TSSOP * Available in Pb (lead) free package * Replaces a spread spectrum clock generator and a * * * * * * buffer Input clock or crystal frequency of 20-34 MHz Output frequency of 20-136 MHz Four spread spectrum clock outputs Duty cycle of 45/55 Operating voltage of 3.3 V Advanced, low power CMOS process Block Diagram VDD 3 4 S3:0 PLL/Clock Synthesis and Spread Spectrum Circuitry 4 CLK1:4 X1/ICLK 20-34 MHz crystal or clock Crystal Oscillator X2 Optional crystal capacitors. GND 3 PDTS MDS 1725 C Integrated Circuit Systems 1 525 Ra ce St ree t, Sa n Jose, CA 9 5126 Revision 021605 tel (40 8) 297-1 201 w w w. i c s t. c o m MK1725 Quad Output Spread Spectrum Clock Generator Pin Assignment X1 S0 S3 VDD GND S1 CLK1 CLK2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 VDD PDTS S2 VDD GND CLK4 CLK3 CLK Output Selection Table S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 1 S0 Multiplier 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 2 2 2 2 4 4 4 4 1 2 4 TEST CLK1:4 Spread % -1% -0.5% +/- 0.5% +/- 0.25% -1% -0.5% +/- 0.5% +/- 0.25% -1% -0.5% +/- 0.5% +/- 0.25% OFF OFF OFF TEST 16 pin (173 mil) TSSOP Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 Pin Name X1 S0 S3 VDD GND S1 CLK1 CLK2 CLK3 Pin Type Input Input Input Power Power Input Output Output Output Pin Description Connect to a 20 - 34 MHz crystal or clock input. Select pin 0. Determines frequency and spread amount on output clocks as per table above. Internal pull-down. Select pin 3. Determines frequency and spread amount on output clocks as per table above. Internal pull-down. Connect to +3.3V. Connect to ground. Select pin 1. Determines frequency and spread amount on output clocks as per table above. Internal pull-down. Clock 1 output. Frequency and spread amount are determined by table above. Weak internal pull-down when tri-state. Clock 2 output. Frequency and spread amount are determined by table above. Weak internal pull-down when tri-state. Clock 3 output. Frequency and spread amount are determined by table above. Weak internal pull-down when tri-state. MDS 1725 C In te grated Circu it Systems 2 52 5 Race Stre et, San Jose, CA 951 26 Revision 021605 te l (4 08) 29 7-120 1 w w w. i c s t . c o m MK1725 Quad Output Spread Spectrum Clock Generator Pin Number 10 11 12 13 14 15 16 Pin Name CLK4 GND VDD S2 Pin Type Output Power Power Input Pin Description Clock 4 output. Frequency and spread amount are determined by table above. Weak internal pull-down when tri-state. Connect to ground. Connect to +3.3V. Select pin 2. Determines frequency and spread amount on output clocks as per table above. Internal pull-down. Power Down Tri-state. Powers down entire chip and tri-states outputs when low. Internal pull-up resistor. Connect to +3.3V. 20MHz-34MHz crystal input. Float for clock input. PDTS VDD X2 Input Power Input External Components Decoupling Capacitor As with any high performance mixed-signal IC, the MK1725 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01F must be connected between each VDD and the PCB ground plane. capacitance, each crystal capacitor would be 24 pF [(18-6) x 2] = 24. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01F decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pins should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI the 33 series termination resistor (if needed) should be placed close to the clock outputs. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the MK1725. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -6)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with an 18 pF load MDS 1725 C In te grated Circu it Systems 3 52 5 Race Stre et, San Jose, CA 951 26 Revision 021605 te l (4 08) 29 7-120 1 w w w. i c s t . c o m MK1725 Quad Output Spread Spectrum Clock Generator Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1725. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 5V Rating -0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 125C 260C Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. 0 +3.135 Typ. +3.3 Max. +70 +3.465 Units C V DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70C Parameter Operating Voltage Supply Current Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Short Circuit Current Input Capacitance Nominal Output Impedance Internal Pull-up Resistor Internal Pull-down Resistor Symbol VDD IDD VIH VIL VIH VIL VOH VOH VOL IOS CIN ZOUT RPU RPD Conditions 20M in S3:0=[0100] Input selects Input selects ICLK ICLK IOH = -4 mA IOH = -12 mA IOL = 12 mA Clock outputs Min. 3.135 2 Typ. 3.3 22 Max. 3.465 Units V mA V 0.8 VDD/2+1 VDD/2-1 VDD-0.4 2.4 0.4 70 5 20 V V V V V V mA pF PDTS pin Clock outputs; S3:0 360 510 k k MDS 1725 C In te grated Circu it Systems 4 52 5 Race Stre et, San Jose, CA 951 26 Revision 021605 te l (4 08) 29 7-120 1 w w w. i c s t . c o m MK1725 Quad Output Spread Spectrum Clock Generator AC Electrical Characteristics Unless stated otherwise, VDD = 3.0 V 5%, Ambient Temperature 0 to +70C Parameter Input Frequency Output Rise Time Output Fall Time Output Clock Duty Cycle Symbol fIN tOR tOF Conditions Crystal or clock input 20% to 80%, Note 1 80% to 20%, Note 1 At VDD/2, Note 1 1X, 2X modes at VDD/2, Note 1 4X mode Min. 20 Typ. 1.2 1.0 Max. Units 34 MHz ns ns 55 60 % % ps 50 250 kHz ps ms ns 45 40 50 50 150 Absolute Clock Period Jitter Modulation Frequency Output to Output Skew Output Enable Time Output Disable Time Note 1: Measured with a 15 pF load. tJ fmod Cycle to cycle, Note 1 25 Non-spread modes PDTS high to output spread profile stable PDTS low to tri-state tOE tOD 2.6 10 Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol JA JA JA JC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. 78 70 68 37 Max. Units C/W C/W C/W C/W Thermal Resistance Junction to Case Marking Diagram 16 9 MK1725GL ###### YYWW 1 Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year and the week number that the part was assembled. 3. "L" denotes Pb (lead) free package. 4. Bottom marking: (origin). Origin = country of origin of not USA. 8 MDS 1725 C In te grated Circu it Systems 5 52 5 Race Stre et, San Jose, CA 951 26 Revision 021605 te l (4 08) 29 7-120 1 w w w. i c s t . c o m MK1725 Quad Output Spread Spectrum Clock Generator Package Outline and Package Dimensions (16 pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters Symbol Min Max Inches Min Max 16 E1 IN D EX AR EA E 1 2 D A A1 A2 b C D E E1 e L aaa -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10 -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004 A 2 A 1 A c -Ce b S E A T IN G P LA N E L aaa C Ordering Information Part / Order Number MK1725GLF MK1725GLFT Marking see page 5 Shipping Packaging Tubes Tape and Reel Package 16-pin TSSOP 16-pin TSSOP Temperature 0 to +70 C 0 to +70 C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 1725 C In te grated Circu it Systems 6 52 5 Race Stre et, San Jose, CA 951 26 Revision 021605 te l (4 08) 29 7-120 1 w w w. i c s t . c o m |
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